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| HPLR3103, HPLU3103 Data Sheet July 1999 File Number 4501.2 52A, 30V, 0.019 Ohm, N-Channel Logic Level, Power MOSFETs These are N-Channel enhancement mode silicon gate power field effect transistors. They are advanced power MOSFETs designed, tested, and guaranteed to withstand a specified level of energy in the breakdown avalanche mode of operation. All of these power MOSFETs are designed for applications such as switching regulators, switching converters, motor drivers, relay drivers, and drivers for high power bipolar switching transistors requiring high speed and low gate drive power. These types can be operated directly from integrated circuits. Features * Logic Level Gate Drive * 52A, 30V * Low On-Resistance, rDS(ON) = 0.019 * UIS Rating Curve * Related Literature - TB334, "Guidelines for Soldering Surface Mount Components to PC Boards" Calculated continuous current based on maximum allowable junction temperature. Package limited to 20A continuous, see Figure 9. Ordering Information PART NUMBER HPLU3103 HPLR3103 PACKAGE TO-251AA TO-252AA BRAND HP3103 HP3103 Symbol D G NOTE: When ordering, use the entire part number. Add the suffix T to obtain the TO-252AA variant in tape and reel, e.g., HPLR3103T. S Packaging JEDEC TO-251AA JEDEC TO-252AA DRAIN (FLANGE) SOURCE DRAIN GATE GATE SOURCE DRAIN (FLANGE) 6-3 CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright (c) Intersil Corporation 1999 HPLR3103, HPLU3103 Absolute Maximum Ratings TC = 25oC, Unless Othewise Specified HPLR3103, HPLU3103 30 30 16V 52 390 240 89 0.71 -55 to 150 300 260 UNITS V V V A A mj W W/oC oC oC oC Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDSS Drain to Gate Voltage (RGS = 20k) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Pulsed Drain Current (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .IDM Single Pulse Avalanche Energy (Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EAS Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG Maximum Temperature for Soldering Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TL Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. TJ = 25oC to 125oC. Electrical Specifications PARAMETER TC = 25oC, Unless Otherwise Specified SYMBOL BVDSS VGS(TH) IDSS TEST CONDITIONS ID = 250A, VGS = 0V VGS = VDS, ID = 250A VDS = 30V, VGS = 0V VDS = 24V, VGS = 0V, TC = 125oC MIN 30 1 VDD = 24V ID 34A, VGS = 4.5V (Figure 6) VDS = 25V, VGS = 0V, f = 1MHz (Figure 5) Measured From the Source Lead, 6mm (0.25in) From Package to Center of Die Measured From the DrainLead, 6mm (0.25in) From Package to Center of Die G LS S TYP 0.037 9 210 20 54 1600 640 320 7.5 MAX 25 250 100 0.019 0.024 50 14 28 - UNITS V V A A nA V ns ns ns ns nC nC nC pF pF pF nH Drain to Source Breakdown Voltage Gate to Source Threshold Voltage Zero Gate Voltage Drain Current Gate to Source Leakage Current Breakdown Voltage Temperature Coefficient Drain to Source On Resistance (Note 3) Turn-On Delay Time Rise Time Turn-Off Delay Time (Note 3) Fall Time Total Gate Charge Gate to Source Charge Gate to Drain "Miller" Charge Input Capacitance Output Capacitance Reverse Transfer Capacitance Internal Source Inductance IGSS VGS = 16V V(BR)DSS Reference to 25oC, ID = 1mA /TJ rDS(ON) ID = 28A, VGS = 10V ID = 23A, VGS = 4.5V td(ON) tr td(OFF) tf Qg Qgs Qgd CISS COSS CRSS LS Modified MOSFET Symbol Showing the Internal Devices Inductances D LD VDD = 15V, ID 34A, RL = 0.441, VGS = 4.5V, RGS =3.4, Ig(REF) = 3mA - Internal Drain Inductance LD - 4.5 - nH 6-4 HPLR3103, HPLU3103 Electrical Specifications PARAMETER Thermal Resistance Junction to Case Thermal Resistance Junction to Ambient TC = 25oC, Unless Otherwise Specified SYMBOL RJC RJA (PCB Mount Steady State) TEST CONDITIONS MIN TYP MAX 1.4 110 50 UNITS oC/W oC/W oC/W Source to Drain Diode Specifications PARAMETER Continuous Source to Drain Current SYMBOL ISD ISDM TEST CONDITIONS MOSFET Symbol Showing The Integral Reverse P-N Junction Diode D MIN - TYP - MAX 52 (Note 1) 220 UNITS A Pulsed Source to Drain Current (Note 2) G - A S Source to Drain Diode Voltage (Note 3) Reverse Recovery Time (Note 3) Reverse Recovered Charge (Note 3) NOTES: VSD trr QRR ISD = 28A ISD = 34A, dISD/dt = 100A/s ISD = 34A, dISD/dt = 100A/s - 81 210 1.3 120 310 V ns nC 2. Repetitive rating; pulse width limited by maximum junction temperature (See Figure 11). 3. Pulse width 300s; duty cycle 2%. 4. VDD = 15V, starting TJ = 25oC, L = 300H, RG = 25, peak IAS = 34A, (Figure 10). Typical Performance Curves 1000 ID, DRAIN TO SOURCE CURRENT (A) VGS IN DECENDING ORDER 15V 12V 10V 8.0V 100 6.0V 4.0V 3.0V 2.5V 10 20s PULSE WIDTH TC = 25oC 1000 ID, DRAIN TO SOURCE CURRENT (A) VGS IN DECENDING ORDER 15V 12V 10V 8.0V 100 6.0V 4.0V 3.0V 2.5V 10 1 0.1 1.0 10 100 1 0.1 20s PULSE WIDTH TC = 150oC 1 10 100 VDS, DRAIN TO SOURCE VOLTAGE (V) VDS, DRAIN TO SOURCE VOLTAGE (V) FIGURE 1. OUTPUT CHARACTERISTICS FIGURE 2. OUTPUT CHARACTERISTICS 6-5 HPLR3103, HPLU3103 Typical Performance Curves 1000 ID, DRAIN TO SOURCE CURRENT(A) VDS = 15V 20s PULSE WIDTH NORMALIZED DRAIN TO SOURCE 2.0 ON RESISTANCE (Continued) 2.5 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX ID = 46A, VGS = 10V 100 TJ = 25oC 1.5 10 TJ = 150oC 1.0 0.5 1 2 3 4 5 6 7 8 9 VGS, GATE TO SOURCE VOLTAGE (V) 0 -80 -40 0 40 80 120 160 TJ, JUNCTION TEMPERATURE (oC) 200 FIGURE 3. TRANSFER CHARACTERISTICS FIGURE 4. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE 3200 2800 C, CAPACITANCE (pF) 2400 2000 1600 1200 800 400 0 1 10 VDS, DRAIN TO SOURCE VOLTAGE (V) 100 COSS CISS VGS, GATE TO SOURCE VOLTAGE (V) VGS = 0V, f = 1MHz CISS = CGS + CGD CRSS = CGD COSS CDS + CGS 20 ID = 34A 16 VDS = 15V 12 VDS = 24V 8 4 CRSS 0 0 10 20 30 40 QG , TOTAL GATE CHARGE (nC) FIGURE 5. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE FIGURE 6. GATE CHARGE WAVEFORMS FOR CONSTANT GATE CURRENT 1000 ISD, REVERSE DRAIN CURRENT(A) PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX ID = 46A, VGS = 10V 1000 ID, DRAIN CURRENT (A) 10s 100 100s OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON) 100 TJ = 175oC TJ = 25oC 10 1ms 10ms 10 0.4 0.8 1.2 1.6 2.0 2.4 2.8 VSD, SOURCE TO DRAIN VOLTAGE (V) 1 1 VDSS MAX = 30V 10 VDS, DRAIN TO SOURCE VOLTAGE (V) 100 FIGURE 7. SOURCE TO DRAIN DIODE FORWARD VOLTAGE FIGURE 8. FORWARD BIAS SAFE OPERATING AREA 6-6 HPLR3103, HPLU3103 Typical Performance Curves 60 (Continued) 1000 IAS, AVALANCHE CURRENT (A) If R = 0 tAV = (L)(IAS)/(1.3*RATED IASVDSS - VDD) If R 0 tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1] EAS POINT STARTING TJ = 25oC 10 ID, DRAIN CURRENT (A) 45 100 30 15 STARTING TJ = 150oC 0 25 50 75 100 125 150 1 TC, CASE TEMPERATURE (oC) 0.001 0.01 1 0.1 tAV, TIME IN AVALANCHE (ms) 10 100 FIGURE 9. MAXIMUM CONTINUOUS DRAIN CURRENT vs CASE TEMPERATURE FIGURE 10. UNCLAMPED INDUCTIVE SWITCHING CAPABILITY 2 1 THERMAL IMPEDANCE ZJC, NORMALIZED DUTY CYCLE - DESCENDING ORDER 0.5 0.2 0.1 0.05 0.02 0.01 PDM t1 SINGLE PULSE t2 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZJC x RJC + TC 10-3 10-2 10-1 t, RECTANGULAR PULSE DURATION (s) 100 101 0.1 0.01 10-5 10-4 FIGURE 11. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE Test Circuits and Waveforms VDS BVDSS L VARY tP TO OBTAIN REQUIRED PEAK IAS VGS DUT tP RG IAS VDD tP VDS VDD + 0V IAS 0.01 0 tAV FIGURE 12. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 13. UNCLAMPED ENERGY WAVEFORMS 6-7 HPLR3103, HPLU3103 Test Circuits and Waveforms VDS RL Qgd Qgs VGS + (Continued) VDD Qg(TOT) VGS VDD DUT IG(REF) IG(REF) 0 0 VDS FIGURE 14. GATE CHARGE TEST CIRCUIT FIGURE 15. GATE CHARGE WAVEFORMS VDS tON td(ON) RL VDS + tOFF td(OFF) tr tf 90% 90% VGS DUT RGS VDD 0 10% 90% 10% VGS VGS 0 10% 50% PULSE WIDTH 50% FIGURE 16. SWITCHING TIME TEST CIRCUIT FIGURE 17. RESISTIVE SWITCHING WAVEFORMS All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (407) 724-7000 FAX: (407) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil (Taiwan) Ltd. 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029 6-8 |
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